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1 of 17 march 26, 2001 ? 2001 integrated device technology, inc. dsc 5349/3 155 mbps atm sar controller with abr support for pci-based networking applications full-duplex segmentation and reassembly (sar) at 155 mbps "wire-speed" (310 mbps aggregate speed) operates with atm networks up to 155.52 mbps stand-alone controller: embedded processor not required performs atm layer protocol functions supports aal5, aal3/4, aal0 and raw cell formats supports constant bit rate (cbr), variable bit rate (vbr), and unassigned bit rate (ubr), and available bit rate (abr) service classes segments and reassembles cs-pdus into host memory up to 256 active transmit connections up to 256 active receive connections abr, vbr, ubr selectable per vc time-out automatic aal5 padding four buffer pools for independent or chained reassembly supports any buffer alignment condition free buffer queues mapped into pci memory space rx fifo size (configurable to 1024 kbytes) configurable transmit fifo depth for reduced latency supports big and little endian data transfers null cell disable option during transmit nand test mode rm cell handling utopia level 1 interface to phy utility bus interface for phy management serial eeprom interface eprom interface pci 2.1 compliant uni 3.1, tm 4.0 compliant meets pci bus power management and interface specification revision 1.1 pin compatible with idt 77211 sar commercial and industrial temperature ranges 208-lead pqfp package (28 x 28mm) software drivers: ? sarwin 2 demonstration program ? ndis driver ? vx works (3rd party) ? linux (3rd party)

the IDT77222 is a member of idt's family of sar products for asyn- chronous transfer mode (atm) networks. the IDT77222 performs both the atm adaptation layer (aal) segmentation and reassembly (sar) function and the atm layer protocol functions. a network interface card (nic) or internetworking product based on the IDT77222 uses host memory, rather than local memory, to reas- semble convergence sublayer protocol data units (cs-pdus) from atm cell payloads received from the network. when transmitting, as cs- pdus become ready, they are queued in host memory and segmented

32 33mhz IDT77222 155mbps pci atm abr sar phy rx utopia bus tx utopia bus utility bus 8 8 82 2 155mbps 16k x 32 sram eeprom 32 80.0mhz osc. pci bus prom 8 5349 drw 01 p c i i n t e r f a c e IDT77222
2 of 17 march 26, 2001 IDT77222 by the IDT77222 into atm cell payloads. from this, the IDT77222 then creates complete 53-byte atm cells which are sent through the network. the IDT77222's on-chip pci bus master interface provides efficient, low latency dma transfers with the host system, while its utopi a interface provides direct connection to phy components used in 25.6 mbps to 155 mbps atm networks. the IDT77222 is fabricated using state-of-the-art cmos technology, providing the highest levels of integ ration, performance and reliability, with the low-power consumption characteristics of cmos.

. / 8 pci interface pci bus transmit control tx utopia interface sram interface receive control rx utopia interface tx utopia bus sram bus rx utopia bus u tility eeprom out 5349 drw 02 / 32 eeprom in / 8 / 8 / 32 1 vcc 2 ad(31) 3 ad(30) 4 ad(29) 5 ad(28) 6 ad(27) 7 ad(26) 8 gnd 9 gnd 10 ad(25) 11 ad(24) 12 c/be(3) 13 idsel 14 ad(23) 15 ad(22) 16 gnd 17 gnd 18 ad(21) 19 vcc 20 ad(20) 21 ad(19) 22 ad(18) 23 ad(17) 24 ad(16) 25 gnd 26 gnd 27 c/be(2) 28 vcc 29 frame 30 irdy 31 trdy 32 devsel 33 stop 34 gnd 35 gnd 36 inta 37 vcc 38 perr 39 serr 40 par 41 c/be(1) 42 ad(15) 43 gnd 44 gnd 45 ad(14) 46 ad(13) 47 ad(12) 48 ad(11) 49 ad(10) 50 ad(9) 51 ad(8) 52 gnd 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 gnd phy_int phy_rst utl_ale utl_rd utl_wr gnd utl_ad(7) utl_ad(6) utl_ad(5) utl_ad(4) vcc utl_ad(3) gnd utl_ad(2) utl_ad(1) utl_ad(0) vcc sar_clk gnd sr_i/o(30) sr_i/o(29) gnd sr_i/o(28) sr_i/o(27) sr_i/o(26) sr_i/o(25) sr_i/o(24) vcc sr_i/o(23) gnd sr_i/o(22) sr_i/o(21) eedo eedi eesclk eecs vcc e_ce sr_i/o(31) sr_i/o(20) sr_i/o(19) sr_i/o(18) sr_i/o(17) gnd sr_i/o(16) sr_i/o(15) sr_i/o(14) sr_i/o(13) sr_i/o(12) sr_i/o(11) vcc 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 1 0 0 1 0 1 1 0 2 1 0 3 1 0 4 v c c g n d c / b e ( 0 ) a d ( 7 ) v c c a d ( 6 ) a d ( 5 ) a d ( 4 ) g n d g n d a d ( 3 ) a d ( 2 ) a d ( 1 ) a d ( 0 ) g n d n / c s r _ w e s r _ a 1 3 s r _ a 8 s r _ a 9 s r _ a 1 1 s r _ o e s r _ a 1 0 s r _ c s n / c g n d n / c v c c s r _ a 1 2 s r _ a 7 s r _ a 6 s r _ a 5 s r _ a 4 s r _ a 3 s r _ a 2 s r _ a 1 s r _ a 0 g n d g n d s r _ i / o ( 0 ) s r _ i / o ( 1 ) s r _ i / o ( 2 ) s r _ i / o ( 3 ) s r _ i / o ( 4 ) s r _ i / o ( 5 ) s r _ i / o ( 6 ) g n d s r _ i / o ( 7 ) s r _ i / o ( 8 ) s r _ i / o ( 9 ) s r _ i / o ( 1 0 ) g n d 208 2 0 7 2 0 6 2 0 5 2 0 4 2 0 3 2 0 2 2 0 1 2 0 0 1 9 9 1 9 8 1 9 7 1 9 6 1 9 5 1 9 4 1 9 3 1 9 2 1 9 1 1 6 1 1 9 0 1 8 9 1 8 8 1 8 7 1 8 6 1 8 5 1 8 4 1 8 3 1 8 2 1 8 1 1 8 0 1 7 9 1 7 8 1 7 7 1 7 6 1 7 5 1 7 4 1 7 3 1 7 2 1 7 1 1 7 0 1 6 9 1 6 8 1 6 7 1 6 6 1 6 5 1 6 4 1 6 3 1 6 2 1 6 0 1 5 9 1 5 8 1 5 7 g n d v c c r e q g n t c l k r s t g n d g n d g n d v c c v c c g n d g n d t x p a r i t y p h y _ c l k r x c l k g n d r x e m p t y / r x c l a v r x e n b r x d a t a ( 7 ) r x d a t a ( 6 ) r x d a t a ( 5 ) r x d a t a ( 4 ) g n d r x d a t a ( 3 ) r x d a t a ( 2 ) r x d a t a ( 1 ) r x d a t a ( 0 ) g n d t x c l k t x f u l l / t x c l a v t x e n b t x s o c g n d t x d a t a ( 7 ) t x d a t a ( 6 ) v c c t x d a t a ( 5 ) t x d a t a ( 4 ) g n d t x d a t a ( 3 ) t x d a t a ( 2 ) t x d a t a ( 1 ) t x d a t a ( 0 ) u t l _ c s ( 1 ) u t l _ c s ( 0 ) v c c index 5349 drw 03 r x s o c n a n d _ e n c l k _ o u t g n d n a n d _ o u t IDT77222 sar controller with abr support 208 pin pqfp pinout pu-208 refer to psc-4053 for detailed package drawing
3 of 17 march 26, 2001 IDT77222

1v cc i power 2 ad(31) i/o pci address/data line 3 ad(30) i/o pci address/data line 4 ad(29) i/o pci address/data line 5 ad(28) i/o pci address/data line 6 ad(27) i/o pci address/data line 7 ad(26) i/o pci address/data line 8 gnd i power 9 gnd i power 10 ad(25) i/o pci address/data line 11 ad(24) i/o pci address/data line 12 c/be(3) i/o pci bus command 13 idsel i pci bus id select 1 52 156 105 53 104 208 157 index 1.228 0.016 (31.2 0.4) 1.10 0.004 (28.0 0.1) 1 . 2 2 8 0 . 0 1 6 ( 3 1 . 2 0 . 4 ) 1 . 1 0 0 . 0 0 4 ( 2 8 . 0 0 . 1 ) 0.02 0.004 (0.5 0.1) 0.008 0.004 (0.2 0.1) 0.024 0.008 (0.6 0.2) 0.063 (1.6) 0.013 0.002 (0.33 0.06) 0.133 0.004 (3.37 0.1) 5349 drw 04
4 of 17 march 26, 2001 IDT77222 14 ad(23) i/o pci address/data line 15 ad(22) i/o pci address/data line 16 gnd i power 17 gnd i power 18 ad(21) i/o pci address/data line 19 v cc i power 20 ad(20) i/o pci address/data line 21 ad(19) i/o pci address/data line 22 ad(18) i/o pci address/data line 23 ad(17) i/o pci address/data line 24 ad(16) i/o pci address/data line 25 gnd i power 26 gnd i power 27 c/be(2) i/o pci bus command 28 v cc i power 29 frame i/o pci cycle frame 30 irdy i/o pci initiator ready 31 trdy i/o pci target ready 32 devsel i/o pci target indicating address decode 33 stop i/o pci target requesting master to stop 34 gnd i power 35 gnd i power 36 inta o pci "interrupt" "a" "request" 37 v cc i power 38 perr i/o pci data parity error 39 serr o pci system error 40 par i/o pci parity (for ad[0:31] and c/be[0:3]) 41 c/be(1) i/o pci bus command 42 ad(15) i/o pci address/data line 43 gnd i power 44 gnd i power 45 ad(14) i/o pci address/data line 46 ad(13) i/o pci address/data line 47 ad(12) i/o pci address/data line 48 ad(11) i/o pci address/data line 49 ad(10) i/o pci address/data line 50 ad(9) i/o pci address/data line 51 ad(8) i/o pci address/data line 52 gnd i power

5 of 17 march 26, 2001 IDT77222 53 v cc i power 54 gnd i power 55 c/be (0) i/o pci bus command 56 ad(7) i/o pci address/data line 57 v cc i power 58 ad(6) i/o pci address/data line 59 ad(5) i/o pci address/data line 60 ad(4) i/o pci address/data line 61 gnd i power 62 gnd i power 63 ad(3) i/o pci address/data line 64 ad(2) i/o pci address/data line 65 ad(1) i/o pci address/data line 66 ad(0) i/o pci address/data line 67 gnd i power 68 n/c no connect 69 sr_we o sram write enable 70 sr_a13 o sram address line 71 sr_a8 o sram address line 72 sr_a9 o sram address line 73 sr_a11 o sram address line 74 sr_oe o sram output enable control 75 sr_a10 o sram address line 76 sr_cs o sram chip select 77 n/c no connect 78 gnd i power 79 n/c no connect 80 v cc i power 81 sr_a12 o sram address line 82 sr_a7 o sram address line 83 sr_a6 o sram address line 84 sr_a5 o sram address line 85 sr_a4 o sram address line 86 sr_a3 o sram address line 87 sr_a2 o sram address line 88 sr_a1 o sram address line 89 sr_a0 o sram address line 90 gnd i power 91 gnd i power

6 of 17 march 26, 2001 IDT77222 92 sr_i/o(0) i/o sram data input/output line 93 sr_i/o(1) i/o sram data input/output line 94 sr_i/o(2) i/o sram data input/output line 95 sr_i/o(3) i/o sram data input/output line 96 sr_i/o(4) i/o sram data input/output line 97 sr_i/o(5) i/o sram data input/output line 98 gnd i power 99 sr_i/o(6) i/o sram data input/output line 100 sr_i/o(7) i/o sram data input/output line 101 sr_i/o(8) i/o sram data input/output line 102 sr_i/o(9) i/o sram data input/output line 103 sr_i/o(10) i/o sram data input/output line 104 gnd i power 105 v cc i power 106 sr_i/o(11) i/o sram data input/output line 107 sr_i/o(12) i/o sram data input/output line 108 sr_i/o(13) i/o sram data input/output line 109 sr_i/o(14) i/o sram data input/output line 110 sr_i/o(15) i/o sram data input/output line 111 sr_i/o(16) i/o sram data input/output line 112 gnd i power 113 sr_i/o(17) i/o sram data input/output line 114 sr_i/o(18) i/o sram data input/output line 115 sr_i/o(19) i/o sram data input/output line 116 sr_i/o(20) i/o sram data input/output line 117 sr_i/o(21) i/o sram data input/output line 118 sr_i/o(22) i/o sram data input/output line 119 gnd i power 120 sr_i/o(23) i/o sram data input/output line 121 v cc i power 122 sr_i/o(24) i/o sram data input/output line 123 sr_i/o(25) i/o sram data input/output line 124 sr_i/o(26) i/o sram data input/output line 125 sr_i/o(27) i/o sram data input/output line 126 sr_i/o(28) i/o sram data input/output line 127 gnd i power 128 sr_i/o(29) i/o sram data input/output line 129 sr_i/o(30) i/o sram data input/output line 130 sr_1/o(31) i/o sram data input/output line

7 of 17 march 26, 2001 IDT77222 131 e_ce o eprom eprom chip select 132 v cc i power 133 eecs o eeprom chip select 134 eesclk o eeprom clock 135 eedi i eeprom data input 136 eedo o eeprom data output 137 gnd i power 138 sar_clk i sar clock input 139 v cc i power 140 utl_ad(0) i/o utility address/data bus 141 utl_ad(1) i/o utility address/data bus 142 utl_ad(2) i/o utility address/data bus 143 gnd i power 144 utl_ad(3) i/o utility address/data bus 145 v cc i power 146 utl_ad(4) i/o utility address/data bus 147 utl_ad(5) i/o utility address/data bus 148 utl_ad(6) i/o utility address/data bus 149 utl_ad(7) i/o utility address/data bus 150 gnd i power 151 utl_wr o utility write control 152 utl_rd o utility read control 153 utl_ale o utility address latch enable 154 phy_rst o phy rest control 155 phy_int i phy interrupt input from phy 156 gnd i power 157 vcc i power 158 utl_cs(0) o utility chip select (0) 159 utl_cs(1) o utility chip select (1) 160 txdata(0) o utopia transmit data bit 0 161 txdata(1) o utopia transmit data bit 1 162 txdata(2) o utopia transmit data bit 2 163 txdata(3) o utopia transmit data bit 3 164 gnd i power 165 txdata(4) o utopia transmit data bit 4 166 txdata(5) o utopia transmit data bit 5 167 v cc i power 168 txdata(6) o utopia transmit data bit 6 169 txdata(7) o utopia transmit data bit 7

8 of 17 march 26, 2001 IDT77222 170 gnd i power 171 txsoc o utopia transmit start of cell 172 txenb o utopia transmit enable control 173 txfull /txclav i utopia transmit buffer full 174 txclk o utopia transmit data sync clock 175 gnd i power 176 rxdata(0) i utopia receive data bit 0 177 rxdata(1) i utopia receive data bit 1 178 rxdata(2) i utopia receive data bit 2 179 rxdata(3) i utopia receive data bit 3 180 gnd i power 181 rxdata(4) i utopia receive data bit 4 182 rxdata(5) i utopia receive data bit 5 183 rxdata(6) i utopia receive data bit 6 184 rxdata(7) i utopia receive data bit 7 185 rxsoc i utopia receive start of cell 186 rxenb o utopia receive enable control 187 rxempty /rxclav i utopia receive buffer empty 188 gnd i power 189 rxclk o utopia receive data sync clock 190 phy_clk i utopia transmit sync clock input 191 txparity o utopia transmit data parity bit 192 gnd i power 193 nand_out o power nand output chain 194 gnd i power 195 gnd i power 196 v cc i power 197 v cc i power 198 clk_out o power sar_clk divided by 3 199 gnd i power 200 gnd i power 201 nand_en i power nand input chain 202 gnd i power 203 rst i pci system bus reset 204 clk i pci bus clock 205 gnt i pci bus grant signal from arbiter 206 req o pci bus request 207 v cc i power 208 gnd i power

9 of 17 march 26, 2001 IDT77222 !" # !" # !" # !" #$ $ $ $ % % % % % % % %
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( ' ( ' ( ' ( ' ( & ( & ( & ( & v cc supply voltage -0.3 6.5 v v in input voltage v ss - 0.3 v cc + 0.3 v v out output voltage v ss - 0.3 v cc + 0.3 v tstg storage temperature -55 125 deg.c v cc supply voltage 4.75 5.25 v v i input voltage 0 v cc v t a operating temperature 0 70 deg.c titr input ttl rise time ? 2 ns titf input ttl fall time ? 2 ns sar_clk sar clock input freq. 155mb/s 77 80 mhz 25mb/s 25 80 mhz phy_clk phy clock input freq. 155mb/s 19.44 40 mhz 25mb/s 3 40 mhz pci_clk pci clock input freq. 33mhz 0 33.3 mhz c in input capacitance except pci bus ? ? 4 pf c out output capacitance all outputs ? ? 6 pf cbid bi-directional capacitance all bi-directional pins ? ? 10 pf cinpci pci bus input capacitance pci bus inputs ? 10 ? pf cclkpci pci bus clock input capacitance ? 5 12 ? pf cidsel pci bus id select input c apaci tance ? ? 8 ? pf vil low-level ttl input voltage ? -0.7v 0.8 ? v vih high-level ttl input voltage ? 2 v cc + 0.2v ? v vol low-level ttl output voltage except pci bus ? 0.4 ? v vol pci bus low-level ttl output voltage pci bus voltage ? 0.55 ? v voh high-level ttl output voltage ? 2.4 ? ? v iol low-level ttl output current: sr_a(18-0) vss + 0.4v 12 ? ? ma
10 of 17 march 26, 2001 IDT77222 ! ! ! !( ' ( ' ( ' ( ' ( & ( & ( & ( & ) ) ) )!) !) !) !) the nand chain provides a simple test to verify that all bond wires are installed correctly and that all pads are correctly sol dered on a pcb. all signal pads are linked in a nand chain, which is enabled by asserting a high, or ?1?, on nand_en (pin 201). asserting a ?1? on the other inputs forces nand_out (pin 193) to ?1?. by successively setting the inputs to ?0?, starting at clk_out (pin 198) and moving to txpari ty (pin 191), nand_out will toggle with each change. 1. apply a "1" to nand_en. 2. set all the i/o's in the chain to "0" and nand_out should be a "1".the connection order of the pins in the chain are shown i n the nand tree pin order table located on the following page. 3. set clk_out to a "0" and the nand_out should be a "0". 4. leaving pin 198 at a "1" set rst (pin 203) to "1" and nand_out should be a "1". 5. repeat for all remaining i/o's in the nand chain. ioh high-level ttl output current: sr_a(18-0) 2.4v -4 ? ? ma iol low-level ttl output current: rxenb , rxclk, txsoc, txdata (7-0), txenb , txparity, txclk, we , oe , cs , sr_d31-0 v ss + 0.4v 6 ? ? ma ioh high-level ttl output current: rxenb , rxclk, txsoc, txdata7-0, txenb , txparity, txclk, sr_we , sr , oe , sr_cs , sr_i/o(31-0) 2.4v -2 ? ? ma iol low-level ttl output current: utl_ad(7-0), utl_rd , utl_wr , utl_ale , utl_cs0/1 , eesclk, eecs, eedo, phy_rst v ss + 0.4v 3 ? ? ma ioh high-level ttl output current: utl_ad(7-0), utl_rd , utl_wr , utl_ale, utl_cs0/1 , eesclk, eecs, eedo, phy_rst 2.4v -1 ? ? ma iil input leakage current v ss v in vdd -1 1 ? ua ityp dynamic supply current ? ? 300 250 ma input pulse levels 0 to 3.0v input rise/fall times 2ns input timing ref. level 1.5v output ref. level 1.5v ac test load see figure below table 1 ac test conditions 1.5v 50 ? i/o z 0 =50 ? 1 2 3 4 20 30 50 100 200 ? tcd (typical, ns) capacitance (pf) 80 5 6 5349 drw 05
11 of 17 march 26, 2001 IDT77222 ! ! ! ! clk_out 198 ad[12] 47 sr_i/o[06] 99 utl_ad[5] 147 rst 203 ad[11] 48 sr_i/o[07] 100 utl_ad[6] 148 clk 204 ad[10] 49 sr_i/o[08] 101 utl_ad[7] 149 gnt 205 ad[9] 50 sr_i/o[09] 102 utl_wr 151 req 206 ad[8] 51 sr_i/o[10] 103 utl_rd 152 ad[31] 2 c/be [0] 55 sr_i/o[11] 106 utl_ale 153 ad[30] 3 ad[7] 56 sr_i/o[12] 107 phy_rst 154 ad[29] 4 ad[6] 58 sr_i/o[13] 108 phy_int 155 ad[28] 5 ad[5] 59 sr_i/o[14] 109 utl_cs[0] 158 ad[27] 6 ad[4] 60 sr_i/o[15] 110 utl_cs[1] 159 ad[26] 7 ad[3] 63 sr_i/o[16] 111 txdata[0] 160 ad[25] 10 ad[2] 64 sr_i/o[17] 113 txdata[1] 161 ad[24] 11 ad[1] 65 sr_i/o[18] 114 txdata[2] 162 c/be [3] 12 ad[0] 66 sr_i/o[19] 115 txdata[3] 163 idsel 13 sr_we 69 sr_i/o[20] 116 txdata[4] 165 ad[23] 14 sr_a[13] 70 sr_i/o[21] 117 txdata[5] 166 ad[22] 15 sr_a[8] 71 sr_i/o[22] 118 txdata[6] 168 ad[21] 18 sr_a[9] 72 sr_i/o[23] 120 txdata[7] 169 ad[20] 20 sr_a[11] 73 sr_i/o[24] 122 txsoc 171 ad[19] 21 sr_oe 74 sr_i/o[25] 123 txenb 172 ad[18] 22 sr_a[10] 75 sr_i/o[26] 124 txclav 173 ad[17] 23 sr_cs 76 sr_i/o[27] 125 txclk 174 ad[16] 24 sr_a[12] 81 sr_i/o[28] 126 rxdata[0] 176 c/be [2] 27 sr_a[7] 82 sr_i/o[29] 128 rxdata[1] 177 frame 29 sr_a[6] 83 sr_i/o[30] 129 rxdata[2] 178 irdy 30 sr_a[5] 84 sr_i/o[31] 130 rxdata[3] 179 trdy 31 sr_a[4] 85 e_ce 131 rxdata[4] 181 devsel 32 sr_a[3] 86 eecs 133 rxdata[5] 182 stop 33 sr_a[2] 87 eesclk 134 rxdata[6] 183 inita 36 sr_a[1] 88 eedi 135 rxdata[7] 184 perr 38 sr_a[0] 89 eedo 136 rxsoc 185 serr 39 sr_i/o[00] 92 sar_clk 138 rxenb 186 par 40 sr_i/o[01] 93 utl_ad[0] 140 rxclav 187 c/be [1] 41 sr_i/o[02] 94 utl_ad[1] 141 rxclk 189 ad[15] 42 sr_i/o[03] 95 utl_ad[2] 142 phy_clk 190 ad[14] 45 sr_i/o[04] 96 utl_ad[3] 144 txparity 191 ad[13] 46 sr_i/o[05] 97 utl_ad[4] 146 table 2 nand tree pin order
12 of 17 march 26, 2001 IDT77222 ( * ( * ( * ( * + & + & + & + & , , , , - - - - '! '! '! '! * * * * ., ., ., ., - / - / - / - / ( ( ( (

* * * * 0, 0, 0, 0, tval clk to output signal valid delay: ad31-0, c/be 3-0, par, frame , irdy , devsel , trdy , stop , perr , serr 211ns tval(ptp) clk to output signal valid delay: req 212ns ton float to signal active delay: ad31-0, c/be 3-0, par, frame , irdy , devsel , trdy , stop , perr , serr 2?ns toff signal active to float delay: ad31-0, c/be 3-0, par, frame , irdy , devsel , trdy , stop , perr , serr ?28ns tsu input setup time to clk: ad31-0, c/be 3-0, par, frame , irdy , devsel , trdy , stop , perr 7?ns tsu(ptp) input setup time to clk: gnt , (req ) 10(12) ? ns th input hold time from clk: ad31-0, c/be 3-0, par, frame , irdy , devsel , trdy , stop , perr , gnt 2 1 1. does not meet pci local bus revision 2.1 timing specification ?ns trst-pwr reset active time after power stable 1 ? ns trst-clk reset active time after clk stable 100 ? ns trst-off reset active to output float delay: ad31-0, c/be 3-0, par, frame , irdy , devsel , trdy , stop , perr , serr ?40ns thigh clock high time 11n ? ns tlow clock low time 11n ? ns t1 txclk, rxclk delay from phy_clk ? 5 ns t2 txdata(7-0), txsoc, txenb , txparity output valid from txclk 1 15 ns t3 txfull /txclav setup time to txclk 10 ? ns t4 txfull /txclav hold time from txclk 3 1 1. does not meet utopia 1 timing specification (af-phy-0017.00) ?ns t5 rxenb output valid from rxclk 1 15 ns t6 rxdata(7-0), rxsoc setup time to rxclk 10 ? ns t7 rxdata(7-0), rxsoc hold time from rxclk 2 1 ?ns t8 rxempty /rxclav setup time to rxclk 10 ? ns t9 rxempty /rxclav hold time from txclk 2 1 ?ns tw1 utl_ale pulse width 25 ? ns tw2 utl_cs0/1 output valid to utl_ale falling edge 25 ? ns tw3 utl_wr output valid from utl_ale falling edge ? 80 ns tw4 utl_cs0/1 pulse width 275 ? ns tw5 utl_wr pulse width 175 ? ns tw6 utl_ale falling edge to utl_wr rising edge 225 ? ns tw7 utl_ad(7-0) address setup time to utl_ale falling edge 30 ? ns tw8 utl_ad(7-0) address hold time from utl_ale falling edge 10 ? ns tw9 utl_ad(7-0) data setup time to utl_wr rising edge 185 ? ns tw10 utl_ad(7-0) data hold time from utl_wr rising edge 10 ? ns tw11 utl_ale falling edge to utl_cs0/1 rising edge 250 ? ns
13 of 17 march 26, 2001 IDT77222 - - - - % % % %& ( & ( & ( & (

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* * * * 2, 2, 2, 2, %!# %!# %!# %!# % % % %& ( & ( & ( & (

* * * * , , , , 3 3 3 3% % % %'# * '# * '# * '# * 4, 4, 4, 4, 3 3 3 3% % % %'# * '# * '# * '# * 5, 5, 5, 5, tr1 utl_ale pulse width 25 ? ns tr2 utl_cs0/1 output valid to utl_ale falling edge 25 ? ns tr3 utl_rd output valid from utl_ale falling edge ? 80 ns tr4 utl_cs0/1 pulse width 250 ? ns tr5 utl_rd pulse width 185 ? ns tr6 utl_ale falling edge to utl_rd rising edge 250 ? ns tr7 utl_ad(7-0) address setup time to utl_ale falling edge 30 ? ns tr8 utl_ad(7-0) address hold time from utl_ale falling edge 10 ? ns tr9 utl_ad(7-0) data setup time to utl_cs0/1 rising edge 80 ? ns tr10 utl_ad(7-0) data hold time from utl_cs0/1 rising edge 10 ? ns tr11 utl_ale falling edge to utl_cs0/1 rising edge 225 ? ns t1 sr_a(18-0) setup time to sr_we falling edge 2 ? ns t2 sr_cs falling edge to sr_we falling edge 0 ? ns t3 sr_cs pulse width 25 ? ns t4 sr_i/o(31-0) setup time to sr_we rising edge 6 ? ns t5 sr_i/o(31-0) hold time from sr_we rising edge 0 ? ns t6 sr_we pulse width 10 ? ns t1 sr_a(18-0) to sr_i/o(31-0) valid 1 1. sr_i/o (31-0) setup and hold times are guaranteed by design when t1 access time is met. ?15ns t2 sr_oe pulse width 25 ? ns t1 sr_i/o(7-0) hold time from e_ce rising edge 0 ? ns t2 e_ce pulse width 75 ? ns t3 sr_a(18-0) change to sr_i/o(7-0) valid ? 70 ns t4 sr_a(18-0) pulse width 75 ? ns t1 sar_clk to output signal valid delay: eecs, eedo, eeclk 100 ? ns software controlled t2 eedi input setup time to sar_clk 10 ? ns software controlled t3 eedi input hold time from sar_clk 0 ? ns software controlled
14 of 17 march 26, 2001 IDT77222 figure 1 the IDT77222 as a pci master ( illustrates a 4-word write operation by the iidt 77222 to host memory) figure 2 the IDT77222 as a pci target (illustrates a 4-word write operation by the host device driver to the idt7 7222) pci_clk (i) frame (o) c/be3-0 (o) ad31-0 (o) add data0 data1 data2 data3 cmd be3-0 irdy (o) trdy (i) req (o) devsel (i) toff ton tval tval (ptp) 5349 drw 06 para pard0 pard1 pard2 pard3 tcyc tlow thigh ton tval tval tval toff tval tval(ptp) toff ton toff tsu tsu tsu tsu(ptp) th th par (o) gnt (i) pci_clk (1) frame (1) c/be3-0 (1) par (1) ad31-0 (1) add data0 data1 data2 data3 cmd be3-0 pard0 pard1 pard2 pard3 para irdy (1) serr (o) trdy (o) perr (o) devsel (1) th tsu 5349 drw 07 tsu tsu tsu th th th toff toff toff tval, ton tval, ton tval, ton tval req (1) req (o)
15 of 17 march 26, 2001 IDT77222 figure 3 utopia bus timing figure 4 utility bus write cycle figure 5 utility bus read cycle phy_clk (i) txdata 7-0 (o) txclk,rxclk (o) txsoc (o) txparity (o) txfull / txclav txenb (o) 5349 drw 08 rxenb (o) rxdata 7-0 (i) rxsoc (i) rxempty / (i) rxclav t1 t2 t5 t7 t9 t6 t8 t3 t4 (i) utl_cs0/1 (o) utl_wr (o) utl_ad(7-0) (i/o) 5349 drw 09 utl_ale (o) tw1 tw3 tw4 tw5 (o) valid data address (o) tw7 tw2 tw10 tw6 tw8 tw11 tw9 utl_cs0/1 utl_rd utl_ad7-0 5349 drw 10 utl_ale tr1 tr3 tr4 tr5 (i) valid data address (o) tr7 tr2 tr8 tr10 tr9 tr2 tr11 tr6
16 of 17 march 26, 2001 IDT77222 figure 6 sram bus write cycle timing figure 7 sram bus read cycle timing figure 8 eprom timing figure 9 eeprom timing & & & & several software vendors have written IDT77222 software drivers for various operating systems. please contact your local idt sa les representa- tive for a vendor list, or send an e-mail to sarhelp@idt.com. idt offers the sarwin2 demo driver and application suite, which can be used to evaluate the IDT77222 when used with a idt nic r eference or evaluation adapter. it may also be used as a reference for sample source code when developing a proprietary device driver. plea s e contact your idt sales representative or send an e-mail to sarhelp@idt.com to obtain a free cd-rom. sr_cs sr_we sr_i/o(31-0) 5349 drw 11 t1 sr_a(18-0) t4 t2 t5 t3 t6 sr_cs sr_oe sr_i/o(31-0) 5349 drw 12 sr_a(18-0) t1 t2 sr_i/o(7-0) 5349 drw 13 sr-a (18-0) t2 valid data t4 e_ce t1 t3 sar_clk eeclk eecs eedi eedo 5349 drw 14 t1 t2 t3
17 of 17 march 26, 2001 IDT77222 corporate headquarters 2975 stender way santa clara, ca 95054 for sales: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com for tech support: email:sarhelp@idt.com phone: 408 - 49 2 - 8 2 0 8 the idt logo is a registered trademark of integrated device technology, inc. )( )()( )( % %% %

& && & 3 33 3 ! ! ! !& && & nic reference and evaluation adapters are available in several form factors. bill of materials (bom) and schematics are availabl e upon request for each of the nic adapters. a list of current nic adapter offerings can be f ound at www.idt.com. note: the micro abr sar user manual provides a detailed description of the 77222 operation and registers. ' '' ' & && & note: refer to psc-4053 for detailed package drawing. refer to errata list for revision history and how to identify revision. % %% %

++ ++ ++ ++ the 77222 pg pack age is the same package as the 77211 pqf . the 7 7222 is a direct replacement to the 77211 sar. to use the 77222 in a 155 mbps application, a 80 mhz oscillator is required (replace the 50 mhz oscillator used with the 77211).
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6 6/24/98: created new document. 9/15/99: updated software section. 6/22/00: added pg-208 to package pinout and added psc-4053 reference. removed industrial temp rating. changed pin name for pin 198. updat ed sram, utility bus, utopia bus, eeprom and pci timing parameters and diagrams. updated ac test conditions section. added information f o r nand tree. changed from advanced to preliminary data sheet. 03/26/01: changed from preliminary to final data sheet. added to and rearranged the features list. package idt nnnnn device type a power nnn speed a a process/ temp. range 155 speed in mps 77222 155mbs atm segmentation & reassembly (sar) controller for the pci local bus 5349 drw 1 5 pg dui 208-pin plastic quad flatpack industrial 208-pin plastic quad flatpack llowpowercmos (blank) commercial

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